Built-in self-test of semiconductor devices in-field gains importance because of higher quality and safety requirements. Because of this, the scope of design for test (DFT) methodologies implemented during chip development extends from production test to in-field test. In order to allow for testing a certain IC device, a built-in self-test (BIST) mechanism may be implemented within an IC. A BIST mechanism is a function that verifies all or a portion of the internal functionality of the IC device under test. Logic circuitry of an IC may be tested using a logic built-in self-test (LBIST) system. LBIST of digital semiconductor devices or sub-modules of it can be used for proving defect freeness of devices in a test environment and in the field. Highest defect coverage can be achieved by scan-based LBIST solutions.
Referring to FIG. 1, a schematic diagram of an example of an LBIST system 10 is shown, comprising a device under test 30, which may be a complete IC or a partition thereof, having a core logic circuitry 12 to be tested and verified. An LBIST controller 54 may for example comprise a pseudo random pattern generator (PRPG) 14, a test point control signal generator 16, an isolation wrapper for functional core inputs and outputs (IOs) 18, a multiple input signature register (MISR) signature generator 20, a stored MISR signature 22, and a comparator 24.
Design for test for an LBIST architecture comprises the core logic circuitry of the device under test 30 being implemented using bistable multivibrator circuits operable to be connected in one or more scan chains 26. A bistable multivibrator circuit is a circuit that has two stable states and is thereby capable of serving as one bit memory. A bistable multivibrator circuit may for example be a flip-flop circuit or a latch. A scan chain is a shift register comprising bistable multivibrators. A “scan enable” signal 32 may be added to a logic circuitry design. When this signal is asserted by the LBIST controller 54, every bistable multivibrator in this design may be connected into a long shift register. However, a variation of this concept may include forming several scan chains for sub-sets of bistable multivibrator circuits instead of one single chain for all. An input 36 may be used for providing data to a scan chain and an output 46 may sequentially provide the state of every bistable multivibrator of the chain. Using the clock signal 44 of the chip, a test pattern may be entered into the chain of bistable multivibrator circuits. Suitable test patterns are generated using the pseudo random pattern generator (PRPG) 14 based on seed values 34 suitable for the device under test 30.
The basic mechanism may enable the LBIST controller by setting an “LBIST enable” signal 28, use a PRPG 14 to generate the input of a scan chain 26 of the device 30, shift test values into the device using the scan chains 26, initiate one or more functional cycles to get a response of the device and shift it into a MISR signature generator 20. The PRPG may for example generate the scan chain input values in advance or on the fly while shifting the values into the scan chains. The signature generator 20 may compress the captured response and generate a MISR signature. A comparison of the received signature with a stored good MISR signature 22 derived from the pseudo random pattern using comparator 24 may provide an information, whether or not the device under test comprises erroneous circuitry. A signal 38 indicating passing or failure and an end of test signal 40 may be generated. Additionally, a number of test points 42, 48, 50, 52 may for example be included in the device designed for test allowing the LBIST controller to apply control signals to the core logic under test using the test point signal generator 16 for controlling the behaviour of the device under test when processing the test pattern, hence influencing how the core logic is tested for erroneous behaviour. This may increase test coverage of potential defects, i.e. the detection ratio between potential defects which can be detected and number of total potential defects. The LBIST controller may for example be connected to an isolation wrapper 18 which may disconnect signal connections of the device under test, i.e. the tested core, from an (untested) rest of the device. This may avoid that the test and MISR signature are disturbed by core input signals with nondeterministic values. It may further prevent that any random output values of the core disturb the functionality of the rest of the device, which is not under test.
LBIST of digital semiconductor devices can be used to prove defect freeness of the device in the field, which is being installed within a product. High defect coverage can be achieved using scan-based LBIST solutions by applying certain sets of test patterns with respect to the control signals applied to certain test points, allowing for increased test coverage.
In order to apply a test pattern to the bistable multivibrator circuits of a scan chain 26, the core's normal functional operation is stopped for at least as many clock cycles as a scan chain comprises elements. However, since a better detection coverage of possible malfunctions may be desired, several test patterns may be applied, therefore stopping the application being executed on the device under test for a long time, for example more than the duration of a clock cycle times length of a scan chain times number of applied test patterns.
The described system does not keep the application context, i.e. the state values of the bistable multivibrator circuits before receiving the described test pattern may be lost, requiring restart of the device from a random or reset state.